Multiple processors in a multiprocessor computing system may share a common memory. This common memory may store data and/or instructions utilized by the processors in the multiprocessor computing system. In order to improve access time to the common memory, the multiprocessor computing system may be designed such that caches are associated with each of the processors. These caches may store data and/or instructions retrieved from the common memory by individual ones of the processors and may store data to be written to the common memory by the processors.
Cache coherency issues may arise when one or more of the caches store its own copy of data associated with a memory location in the common memory. For example, a first processor in the multiprocessor system may be associated with a first cache and a second processor in the multiprocessor system may be associated with a second cache. The first cache may store a copy of data at memory address 0x66 of the common memory and the second cache may also store a copy of data at memory address 0x66 of the common memory. In this example, a cache coherency issue may arise when the first processor writes new data to memory address 0x66. When the first processor writes new data to memory address 0x66, the copy of the data at memory address 0x66 that is stored in the second cache is now obsolete. In other words, the first cache and the second cache are no longer coherent with respect to memory address 0x66. If the second processor were to use this obsolete copy of the data, the second processor may perform an incorrect behavior.
Typical multiprocessor computing systems include hardware to prevent cache coherency issues. For example, multiprocessor computing systems may implement a directory-based cache coherence mechanism. In a directory-based cache coherence mechanism, a multiprocessor computing system maintains a directory that specifies which caches contain which data. Cache controllers reference the directory when updating data within a cache to ensure the update is made within the other caches. In another example, multiprocessor computing systems may implement a snooping cache coherence mechanism. In a snooping cache coherence mechanism, a centralized hardware component, or each cache, monitors address lines to detect accesses to common memory locations. When a given cache detects a write request to a memory address that the cache has currently cached, the cache may invalidate a cache block in the cache associated with the memory address.
Implementations of directory-based and snooping cache coherence mechanisms may require significant amounts of hardware. As a result, multiprocessor computing systems that implement either of these cache coherence mechanisms may consume significant amounts of additional electrical power and/or may be physically larger.